1 ltc1520 50mbps precision quad line receiver descriptio n u n precision propagation delay: 18ns 3ns over temperature n data rate: 50mbps n low t plh /t phl skew: 500ps typ n low channel-to-channel skew: 400ps typ n rail-to-rail input common mode range n high input resistance: 3 18k, even when unpowered n hot swap capable n can withstand input dc levels of 10v n short-circuit protected n single 5v supply n lvds compatible n will not oscillate with slow input signals features + + + + ltc1520 1520 ta01 3.3k 5v 3.3k 0.01 m f ltc1520 ta02 v in = 1v/div v out = 5v/div ? 5 15 time (ns) 25 35 0 1020304045 receiver input v id = 500mv receiver output v dd = 5v high speed backplane receiver propagation delay guaranteed to fall within shaded area ( 3ns) typical applicatio n u applicatio n s u n high speed backplane interface n line collision detector n pecl and lvds line receivers n level translator n ring oscillator n tapped delay line , ltc and lt are registered trademarks of linear technology corporation. the ltc ? 1520 is a high speed, precision differential line receiver that can operate at data rates as high as 50mbps. a unique architecture provides very stable propagation delays and low skew over a wide input common mode, input overdrive and ambient temperature range. propaga- tion delay is 18ns 3ns, while typically t plh /t phl skew is 500ps and channel-to-channel skew is 400ps. each receiver translates differential input levels (v id 3 100mv) into valid cmos and ttl output levels. its high input resistance ( 3 18k) allows many receivers to be con- nected to the same driver. the receiver outputs go into a high impedance state when disabled. protection features include thermal shutdown and a con- trolled maximum short-circuit current (50ma max) that does not oscillate in and out of short-circuit mode. input resistance remains 3 18k when the device is unpowered or disabled, thus allowing the ltc1520 to be hot swapped into a backplane without loading the data lines. the ltc1520 operates from a single 5v supply and draws 12ma of supply current. the part is available in a 16-lead narrow so package.
2 ltc1520 a u g w a w u w a r b s o lu t exi t i s wu u package / o rder i for atio order part number (note 1) supply voltage ....................................................... 10v digital input currents ..................... C 100ma to 100ma digital input voltages ............................... C 0.5v to 10v receiver input voltages ........................................ 10v receiver output voltages ............. C 0.5v to v dd + 0.5v short-circuit duration .................................... indefinite operating temperature range .................... 0 c to 70 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c ltc1520cs t jmax = 150 c, q ja = 90 c/ w consult factory for industrial and military grade parts. top view s package 16-lead plastic so 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 b1 a1 out 1 enable out 2 a2 b2 gnd v dd b4 a4 out 4 nc out 3 a3 b3 symbol parameter conditions min typ max units v cm input common mode voltage a, b inputs l C 0.2 v dd + 0.2 v v ih input high voltage enable input l 2v v il input low voltage enable input l 0.8 v i in1 input current enable input l C1 1 m a i in2 input current (a, b) v a , v b = 5v l 250 m a v a , v b = 0 l C 250 m a r in input resistance (figure 5) C 0.2v v cm v dd + 0.2v l 18 k w c in a, b input capacitance (note 4) 3 pf v oc open-circuit input voltage (figure 5) v dd = 5v (note 4) l 3.2 3.3 3.4 v v id(min) differential input threshold voltage C 0.2v < v cm < v dd + 0.2v l C 0.1 0.1 v dv id input hysteresis v cm = 2.5v l 20 mv v oh output high voltage i out = C 4ma, v id = 0.1v, v dd = 5v l 4.6 v v ol output low voltage i out = 4ma, v id = 0.1v, v dd = 5v l 0.4 v i ozr three-state output current 0v v out v dd l C10 10 m a i dd total supply current all 4 receivers v id 3 0.1v, no load, enable = 5v l 12 20 ma i osr short-circuit current v out = 0v, v out = v dd l C50 50 ma cmrr common mode rejection ratio v cm = 2.5v, f = 25mhz 45 db v dd = 5v 5% (notes 2, 3) per receiver, unless otherwise noted. dc electrical characteristics
3 ltc1520 symbol parameter conditions min typ max units t plh , t phl input-to-output propagation delay c l = 15pf (figure 1) l 15 18 21 ns t r , t f rise/fall times c l = 15pf 2.5 ns t skd ? t plh C t phl ? skew c l = 15pf, same receiver (note 5) l 500 ps t zl enable to output low c l = 15pf (figure 2) l 10 35 ns t zh enable to output high c l = 15pf (figure 2) l 10 35 ns t lz disable from output low c l = 15pf (figure 2) l 20 35 ns t hz disable from output high c l = 15pf (figure 2) l 20 35 ns t ch-ch channel-to-channel skew c l = 15pf (figure 3) (note 6) l 400 ps t pkg-pkg package-to-package skew c l = 15pf, same temperature 1.5 ns (figure 4, note 4) minimum input pulse width (note 4) 12 ns f in maximum input frequency (note 4) 40 mhz v dd = 5v 5% (notes 2, 3) v id = 500mv, v cm = 2.5v, unless otherwise noted. switchi g ti e characteristics uw the l denotes specifications which apply over the full operating temperature range. note 1: absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. recommended: v dd = 5v 5%. note 2: all currents into the device pins are positive; all currents out of the device pins are negative. note 3: all typicals are given for v dd = 5v, t a = 25 c. note 4: guaranteed by design, but not tested. note 5: worst-case ? t plh C t phl ? skew for a single receiver in a package over the full operating temperature range. note 6: maximum difference between any two t plh or t phl transitions in a single package over the full operating temperature range. typical perfor m a n ce characteristics u w propagation delay (t plh /t phl ) vs temperature temperature ( c) 50 ?5 0 propagation delay (ns) 10 25 0 50 75 ltc1520 g01 5 20 15 25 100 125 v cm = 2.5v v id = 500mv propagation delay (t plh /t phl ) vs input overdrive input overdrive (v) 0.05 0 propagation delay (ns) 15 20 25 0.1 1 5 10 1520 g02 10 5 t a = 25 c v cm = 2.5v propagation delay (t plh /t phl ) vs input common mode input common mode (v) 0 0 propagation delay (ns) 15 2 4 5 ltc1520 g03 10 5 13 20 25 t a = 25 c v id = 500mv
4 ltc1520 typical perfor m a n ce characteristics u w frequency (mhz) 0 supply current (ma) 25 20 15 10 5 0 20 1520 g07 5 10 15 25 100 c 25 c 0 c ?5 c 1 receiver switching supply current vs temperature and frequency frequency (mhz) 0 duty cycle (%) 10 20 25 50.0 49.5 49.0 48.5 48.0 47.5 47.0 46.5 46.0 45.5 1520 g09 515 v in = 50% duty cycle temperature ( c) ?0 skew (ps) 400 390 380 370 360 350 340 10 30 50 70 1520 g08 90 110 skew vs temperature (t skd ) output duty cycle vs frequency frequency (hz) 10 42.0 common mode rejection ratio (db) 42.5 43.5 44.0 44.5 46.5 ltc1520 g04 43.0 1k 100k 10m 45.0 45.5 46.0 t a = 25 c cmrr vs frequency frequency (mhz) 0 supply current (ma) 50 45 40 35 30 25 20 15 10 5 0 20 1520 g05 5 10 15 25 all 4 receivers switching 1 receiver switching supply current vs frequency propagation delay vs load capacitance (t plh /t phl ) load capacitance (pf) 5 propagation delay (ns) 30 25 20 15 10 5 0 15 25 35 55 1520 g06 105 205 t a = 25 c v id = 500mv v cm = 2.5v b1 (pin 1): receiver 1 inverting input. a1 (pin 2): receiver 1 noninverting input. ro1 (pin 3): receiver 1 output. enable (pin 4): receiver output enable pin. a logic high input enables the receiver outputs. a logic low input forces the receiver outputs into a high impedance state. do not float. ro2 (pin 5): receiver 2 output. a2 (pin 6): receiver 2 noninverting input. b2 (pin 7): receiver 2 inverting input. gnd (pin 8): ground pin. a ground plane is recommended for all ltc1520 applications. b3 (pin 9): receiver 3 inverting input. a3 (pin 10): receiver 3 noninverting input. ro3 (pin 11): receiver 3 output. nc (pin 12): no connection. ro4 (pin 13): receiver 4 output. a4 (pin 14): receiver 4 noninverting input. b4 (pin 15): receiver 4 inverting input. v dd (pin 16): 5v supply pin. this pin should be decoupled with a 0.1 m f ceramic capacitor as close as possible to the pin. recommended: v dd = 5v 5%. pi n fu n ctio n s uuu
5 ltc1520 switchi g ti e wavefor s uw w figure 1. propagation delay test circuit and waveforms 2.5v 2.5v v dd /2 v dd /2 3v 2v input output t plh t phl 1520 f01 + input 2.5v output 15pf 1520 f01b 1/4 ltc1520 figure 2. receiver enable and disable timing test circuit and waveforms 1.5v 1.5v 1.5v c l 1k 1k s1 s2 t zh t zl 1.5v t lz 0.2v 0.2v t hz v dd output normally low output normally high 0v 3v enable 5v v ol v oh 0v receiver output out 1 out 1 1520 f02 v dd /2 v dd /2 v dd /2 v dd /2 3v b1, b2 = 2.5v 2v ch1 out input a1, a2 ch2 out t ch-ch t ch-ch 1520 f03 figure 3. any channel to any channel skew, same package figure 4. package-to-package propagation delay skew same input for both packages input a1, b1 v id = 500mv package 1 out 1 1520 f04 t pkg-pkg t pkg-pkg package 2 out 1 equivale t i put networks u u 3.3v 3 18k 3 18k a b receiver enabled, v dd = 5v receiver disabled or v dd = 0v 3.3v 3 18k a b 1520 f05 3 18k figure 5. input thevenin equivalent
6 ltc1520 applicatio n s i n for m atio n wu u u theory of operation unlike typical line receivers whose propagation delay can vary by as much as 500% from package to package and show significant temperature drift, the ltc1520 employs a novel architecture that produces a tightly controlled and temperature compensated propagation delay. the differ- ential timing skew is also minimized between rising and falling output edges, and the propagation delays of any two receivers within a package are very tightly matched. the precision timing features of the ltc1520 reduce overall system timing constraints by providing a narrow 6ns window during which valid data appears at the re- ceiver output. this output timing window applies to all receivers in separate packages over all operating tempera- tures thereby making the ltc1520 well suited for high speed parallel data transmission applications such as backplanes. in clocked data systems, the low skew minimizes duty cycle distortion of the clock signal. the ltc1520 can propagate signals at frequencies up to 25mhz (50mbps) with less than 5% duty cycle distortion. when a clock signal is used to retime parallel data, the maximum recom- mended data transmission rate is 25mbps to avoid timing errors due to clock distortion. rail-to-rail input common mode range enables the ltc1520 to be used in both single-ended and differential applica- tions with transmission distances up to 100 feet. thermal shutdown and short-circuit protection prevent latchup damage to the ltc1520 during fault conditions. single-ended applications over short distances, the ltc1520 can be configured to receive single-ended data by tying one input to a fixed bias voltage and connecting the other input to the driver output. in such applications, standard high speed cmos logic may be used as a driver for the ltc1520. the receiver trip points may be easily adjusted to accommodate different driver output swings by changing the resistor divider at the fixed input. figure 6a shows a single-ended receiver configuration with the driver and receiver connected via pc traces. note that at very high speeds, transmission line and driver ringing effects have to be considered. motorolas mecl system design handbook serves as an excellent reference for transmission line and termination effects. to mitigate transmission errors and duty cycle distortion due to driver ringing, a small output filter or a dampening resistor on v dd may be needed as shown in figure 6b. to transmit single-ended data over distances up to 10 feet, twisted pair is recommended with the unused wire grounded at both ends (figure 7). figure 7. medium distance single-ended transmission using a cmos driver + 1/4 ltc1520 10-ft twisted pair mc74act04 mc74ac04 0.01 m f 120 w 3.3k 5v 2.2k 1520 f07 figure 6b. techniques to minimize driver ringing 10 w pc trace or pc trace 0.01 m f mc74ac04 1520 f06b 10pf 10 w figure 6a. single-ended receiver + 2.2k 5v pc trace 1/4 ltc1520 mc74act04 (ttl input) mc74ac04 (cmos input) 2.2k 1520 f06a 0.01 m f differential transmission the ltc1520 is well suited for medium distance differen- tial transmission due to its rail-to-rail input common mode range. clock rates up to 25mhz can be transmitted over 100 feet of high quality twisted pair. figure 8 shows the
7 ltc1520 applicatio n s i n for m atio n wu u u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. figure 10. temperature stable ring oscillators + + 1/4 ltc1520 + 1/4 ltc1520 9.3mhz oscillator with better than 45/55 duty cycle typical stability 5% over temperature 1/4 ltc1520 3.3k 5v 0.01 m f 3.3k + + 1/4 ltc1520 + 1/4 ltc1520 + 1/4 ltc1520 6.9mhz oscillator output 1/4 ltc1520 0.01 m f 1520 f10 layout considerations a ground plane is recommended when using a high frequency device like the ltc1520. a 0.1 m f ceramic by- pass capacitor less than 1/4 inch away from the v dd pin is also recommended. good bypassing is especially needed when all four channels are driven simultaneously by the same input. under these conditions, and with a bypass capacitor more than 1 1/4 inches away from the v dd pin, the parasitic inductances will cause ringing in the v dd and output pins. this in turn can cause false triggering of the output short-circuit detector (figure 11). when the by- pass capacitor is placed close to the v dd pin, however, the ltc1520 operates normally (figure 12). figure 9. tapped delay line with 18ns steps + 0ns delay input 1/4 ltc1520 + 18ns delay 1/4 ltc1520 + 36ns delay 1/4 ltc1520 + 54ns delay 72ns delay 1/4 ltc1520 3.3k 5v 0.01 m f 3.3k 1520 f09 100-ft twisted pair *mc10116 r t 120 w 1520 f08 100 w 100 w 100 w 5v 5v 5v * 100 w + 1/4 ltc1520 figure 8. differential transmission over long distances ltc1520 receiving differential data from a pecl driver. as in the single-ended configurations, care must be taken to properly terminate the differential data lines to avoid unwanted reflections, etc. alternate uses the tightly controlled propagation delay of the ltc1520 allows the part to serve as a fixed delay element. figure 9 shows the ltc1520 used as a tapped delay line with 18ns 3ns steps. several ltc1520s may be connected in series to form longer delay lines. each tap in the delay line is accurate to within 17% over temperature. as shown in figure 10, the ltc1520 can be used to create a temperature stable ring oscillator with period incre- ments of 36ns. low skew and good channel-to-channel matching enable this oscillator to achieve better than a 45/ 55 duty cycle (the duty cycle approaches 50/50 as more ltc1520s are used for lower frequencies). note that the fixed voltage bias may either be created externally with a resistor divider or generated internally using a bypass capacitor and the internal open circuit bias point (approxi- mately 3.3v). the use of the internal bias point will result in a 1% to 2% distortion of the duty cycle.
8 ltc1520 ? linear technology corporation 1996 1520fs, sn1520 lt/gp 0996 7k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 part number description comments ltc486/487 low power quad rs485 drivers 10mbps, C 7v to 12v common mode range ltc488/489 low power quad rs485 receivers 10mbps, C 7v to 12v common mode range lt ? 1016 ultrafast precision comparator single 5v supply, 10ns propagation delay ltc1518 high speed quad rs485 receiver 50mbps, C 7v to 12v common mode range ltc1519 high speed quad rs485 receiver 50mbps, C 7v to 12v common mode range related parts applicatio n s i n for m atio n wu u u 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) 1 2 3 4 5 6 7 8 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.386 ?0.394* (9.804 ?10.008) 0.228 ?0.244 (5.791 ?6.197) 12 11 10 9 s16 0695 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side package descriptio n u figure 11. v dd bypassing > 1 1/4 away figure 12. v dd bypassing < 3/8 away s package 16-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 1520 f11 50ns/div 1v/div 0v receiver output all 4 receivers driven by the same input input voltage (v) 0 oscillator frequency (khz) 160 150 140 130 120 110 100 90 80 40 10 20 30 50 1520 f12 50ns/div 1v/div 0v receiver output all 4 receivers driven by the same input
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